The present invention relates to a parity bit memory simulator which uses a single bit memory of fixed address length as a parity bit memory to provide and store parity bits for the computer system and to improve the error detection function by means of the operation of its internal detector.
FIG. 1 shows the system block diagram of a conventional memory module, in which the address length of the data memory 10 is equal to that of the parity bit memory 20. Therefore, when the system 15 writes data in the data memory 10 through the data bus 11 or the data memory 10 outputs data to the data bus 11, the parity bit memory 20 simultaneously inputs or outputs the corresponding parity bit signal through the parity bit signal line 13. The signals transmitted by the parity bit signal line 13 and the data bus 11 are outputted or inputted according to the address assigned by the address bus 12 and the recognition control made by the read/write control signal line 14, to further read data out of or store data in the data memory 10 and the parity bit memory 20 respectively. As illustrated, this type of conventional memory module is comprised of a data memory 10 and a parity bit memory 20 of equal address length but different bit lengths. Therefore, this type of conventional memory module has only the function for the storage of parity bits for system recognition but does not have any error detecting ability. If there is any erroneous written in a specific address, the system can find such an error only when the data in the same address is fetched again. Therefore, this type of conventional memory module is less efficient in response to the writing of erroneous data.